library ieee;
use ieee.std_logic_1164.all;

entity FlipFlopTb is
	
end entity FlipFlopTb;

architecture TB of FlipFlopTb is
	
	component dFlipFlop 
	
		port (d, clk, clr_al : in bit;
			q, qn : out bit
		);
		
	end component;
	
	for all : dFlipFlop use entity work.dFlipFlop(DATAFLOW);
		
	signal clk : bit := '1';
	signal clr : bit := '1';
	signal d_in : bit := '0';
	
	signal q, qn : bit;
	
begin

	clk <= NOT clk after 10 ns;
	
	UUT : dFlipFlop port map(d_in, clk, clr, q, qn);
		
	P : process 
		begin
		
			wait for 10 ns;
			
			d_in <= '1';
			wait for 150 ns;
			d_in <= '0';
			wait for 150 ns;
			d_in <= '1';
			
	end process;

end architecture TB;